Changelog for the Clash project
1.2.5 November 9th 2020
Fixed:
- The normalizeType function now fully normalizes types which require calls to
reduceTypeFamily #1469
flogBaseSNat
, clogBaseSNat
and logBaseSNat
primitives are now implemented correctly.Previously these primitives would be left unevaluated causing issues as demonstrated in #1479
- Specializing on functions with type family arguments no longer fails #1477
satSucc
, satPred
correctly handle “small types” such as Index 1
.
msb
no longer fails on values larger than 64 bits
undefined
can now be used as a reset value of autoReg@Maybe
#1507
- Signal’s
fmap
is now less strict, preventing infinite loops in very specific situations. See #1521
- Clash now uses correct function names in manifest and sdc files #1533
- Clash no longer produces erroneous HDL in very specific cases #1536
- Usage of
fold
inside other HO primitives (e.g., map
) no longer fails #1524
1.2.4 July 28th 2020
- Changed:
- Relaxed upper bound versions of
aeson
and dlist
, in preparation for the new Stack LTS.
- Reverted changes to primitive definitions for ‘zipWith’, ‘map’, ‘foldr’, and ‘init’ introduced in 1.2.2. They have shown to cause problems in very specific circumstances.
1.2.3 July 11th 2020
-
Changed:
- Upgrade to nixos 20.03. Nix and snap users will now use packages present in 20.03.
-
Added:
instance Monoid a => Monoid (Vec n a)
instance Text.Printf(Index)
instance Text.Printf(Signed)
instance Text.Printf(Unsigned)
-
Fixed:
- Clash renders incorrect VHDL when GHCs Worker/Wrapper transformation is enabled #1402
- Minor faults in generated HDL when using annotations from
Clash.Annotations.SynthesisAttributes
- Cabal installed through Snap (
clash.cabal
) can now access the internet to fetch pacakges. [#1411]https://github.com/clash-lang/clash-compiler/issues/1411
- Generated QSys file for
altpll
incompatible with Quartus CLI (did work in Quartus GUI)
- Clash no longer uses component names that clash with identifiers imported
from:
1.2.2 June 12th 2020
-
Changed:
- The hardwired functions to unroll primitive definitions for ‘zipWith’, ‘map’, ‘foldr’, and ‘init’ have been changed to only unroll a single step, whereas they would previously unroll the whole definition in one step. This allows Clash to take advantage of the lazy nature of these functions, in turn speeding up compilation speeds significantly in some cases. Part of PR 1354.
-
Added:
- Support for GHC 8.10
- Ability to load designs from precompiled modules (i.e., stored in a package database). See #1172
- Support for ‘-main-is’ when used with
--vhdl
, --verilog
, or --systemverilog
- A partial instance for
NFDataX (Signal domain a)
-
Fixed:
- Clash’s evaluator now inlines work free definitions, preventing situations where it would otherwise get stuck in an infinite loop
caseCon
doesn’t apply type-substitution correctly #1340
- Clash generates illegal SystemVerilog slice #1313
- Fix result type of head and tail Verilog blackboxes #1351
- Certain recursive let-expressions in side a alternatives of a case-expression throw the Clash compiler into an infinite loop #1316
- Fixes issue with one of Clash’s transformations,
inlineCleanup
, introducing free variables #1337
- Fails to propagate type information of existential type #1310
- Certain case-expressions throw the Clash compiler into an infinite loop #1320
- Added blackbox implementation for ‘Clash.Sized.Vector.iterateI’, hence making it usable as a register reset value #1240
iterate
and iterateI
can now be used in reset values #1240
- Prim evaluation fails on undefined arguments #1297
- Missing re-indexing in (Un)Signed fromSLV conversion #1292
- VHDL: generate a type qualification inside ~TOBV, fixes #1360
1.2.1 April 23rd 2020
-
Changed:
- Treat
Signed 0
, Unsigned 0
, Index 1
, BitVector 0
as unit. In effect this means that ‘minBound’ and ‘maxBound’ return 0, whereas previously they might crash #1183
- Infix use of
deepseqX
is now right-associative
-
Added:
- Add ‘natToInteger’, ‘natToNatural’, and ‘natToNum’. Similar to ‘snatTo*’, but works solely on a type argument instead of an SNat.
Clash.Sized.Vector.unfoldr
and Clash.Sized.Vector.unfoldrI
to construct vectors from a seed value
- Added NFDataX instances for
Data.Monoid.{First,Last}
-
Fixed:
- The Verilog backend can now deal with non-contiguous ranges in custom bit-representations.
- Synthesizing BitPack instances for type with phantom parameter fails #1242
- Synthesis of
fromBNat (toBNat d5)
failed due to unsafeCoerce
coercing from Any
- Memory leak in register primitives #1256
- Illegal VHDL slice when projecting nested SOP type #1254
- Vivado VHDL code path (
-fclash-hdlsyn Vivado
) generates illegal VHDL #1264
1.2.0 March 5th 2020
As promised when releasing 1.0, we’ve tried our best to keep the API stable. We
think most designs will continue to compile with this new version, although special
care needs to be taken when using:
-
Use inline blackboxes. Instead of taking a single HDL, inline primitives now
take multiple. For example, InlinePrimitive VHDL ".."
must now be written
as InlinePrimitive [VHDL] ".."
.
-
Use the Enum
instance for BitVector
, Index
, Signed
, or Unsigned
, as
they now respect their maxBound
. See #1089.
On top of that, we’ve added a number of new features:
-
makeTopEntity
: Template Haskell function for generating TopEntity annotations. See the documentation on Haddock for more information.
-
Clash.Explicit.SimIO
: ((System)Verilog only) I/O actions that can be translated to HDL I/O. See the documentation on Haddock for more information.
-
Clash.Class.AutoReg
: A smart register that improves the chances of synthesis tools inferring clock-gated registers, when used. See the documentation on Haddock for more information.
The full list of changes follows. Happy hacking!
1.0.0 September 3rd 2019
0.99.3 July 28th 2018
-
Fixes bugs:
- Evaluator recognizes
Bit
literals #329
- Use existential type-variables in context of GADT pattern match
- Do not create zero-bit temporary variables in generated HDL
- Use correct arguments in nested primitives #323
- Zero-constructor data type needs 0 bits #238
- Create empty component when result needs 0 bits
- Evaluator performs BigNat arithmetic
-
Features:
- Bundle and BitPack instances up to and including 62-tuples
- Handle undefined writes to RAM properly
- Handle undefined clock enables properly
0.99.1 May 12th 2018
- Allow
~NAME[N]
tag inside ~GENSYM[X]
- Support HDL record selector generation #313
InlinePrimitive
support: specify HDL primitives inline with Haskell code
- Support for
ghc-typelits-natnormalise-0.6.1
Lift
instances for TopEntity
and PortName
InlinePrimitive
support: specify HDL primitives inline with Haskell code
0.99 March 31st 2018
- New features:
- Major API overhaul: check the migration guide at the end of
Clash.Tutorial
- New features:
- Explicit clock and reset arguments
- Rename
CLaSH
to Clash
- Implicit/
Hidden
clock and reset arguments using a combination of
reflection
and ImplicitParams
.
- Large overhaul of
TopEntity
annotations
- PLL and other clock sources can now be instantiated using regular functions:
Clash.Intel.ClockGen
and Clash.Xilinx.ClockGen
.
- DDR registers:
- Generic/ASIC:
Clash.Explicit.DDR
- Intel:
Clash.Intel.DDR
- Xilinx:
Clash.Intel.Xilinx
Bit
is now a newtype
instead of a type
synonym and will be mapped to
a HDL scalar instead of an array of one (e.g std_logic
instead of
std_logic_vector(0 downto 0)
)
- Hierarchies with multiple synthesisable boundaries by allowing more than one
function in scope to have a
Synthesize
annotation.
- Local caching of functions with a
Synthesize
annotation
Bit
type is mapped to a HDL scalar type (e.g. std_logic
in VHDL)
- Improved name preservation
- Zero-bit values are filtered out of the generated HDL
- Improved compile-time computation
- Many bug fixes
Older versions
Check out: