Synthesizable Verilog DSL supporting for multiple clock and reset
|Latest on Hackage:||0.1.0|
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HsVerilog: Synthesizable Verilog DSL supporting for multiple clock and reset
Install this from Hackage.
cabal update && cabal install hsverilog
Syntax is similar to Verilog. See tests/test.hs and following examples.
circuit "counter" $ do clk <- input "clk" Bit rstn <- input "rstn" Bit _ <- output "dout" $ 7><0 reg "dout" (7><0) [Posedge clk,Negedge rstn] $ \dout -> If (Not (S rstn)) 0 $ If (Eq dout 7) 0 (dout + 1)
- First Release