hsverilog

Synthesizable Verilog DSL supporting for multiple clock and reset

Latest on Hackage:0.1.0

This package is not currently in any snapshots. If you're interested in using it, we recommend adding it to Stackage Nightly. Doing so will make builds more reliable, and allow stackage.org to host generated Haddocks.

BSD3 licensed by Junji Hashimoto

HsVerilog: Synthesizable Verilog DSL supporting for multiple clock and reset

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Getting started

Install this from Hackage.

cabal update && cabal install hsverilog

Usage

Syntax is similar to Verilog. See tests/test.hs and following examples.

counter circuit

circuit "counter" $ do
  clk <- input "clk" Bit
  rstn <- input "rstn" Bit
  _ <- output "dout" $ 7><0
  reg "dout" (7><0) [Posedge clk,Negedge rstn] $ \dout ->
    If (Not (S rstn)) 0 $
      If (Eq dout 7) 
        0
        (dout + 1)

Changes

0.1.0

  • First Release
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