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PayPrinResidual :: AccountName -> [BondName] -> ActionHastructure Waterfall pay principal regardless predefined balance schedule
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clash-prelude Clash.Explicit.BlockRam Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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clash-prelude Clash.Explicit.BlockRam Primitive for trueDualPortBlockRam
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clash-prelude Clash.Explicit.Prelude Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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clash-prelude Clash.Explicit.Prelude.Safe Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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clash-prelude Clash.Prelude Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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clash-prelude Clash.Prelude.BlockRam Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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clash-prelude Clash.Prelude.Safe Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.
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coinor-clp Numeric.COINOR.CLP No documentation available.
residual :: Compensable a => Lens' (Compensated a) acompensated Numeric.Compensated This Lens lets us edit the residual directly, leaving the primal untouched.