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  1. trueDualPortBlockRam :: forall (nAddrs :: Nat) (domA :: Domain) (domB :: Domain) a . (HasCallStack, KnownNat nAddrs, KnownDomain domA, KnownDomain domB, NFDataX a) => Clock domA -> Clock domB -> Signal domA (RamOp nAddrs a) -> Signal domB (RamOp nAddrs a) -> (Signal domA a, Signal domB a)

    clash-prelude Clash.Explicit.Prelude

    Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.

  2. trueDualPortBlockRam :: forall (nAddrs :: Nat) (domA :: Domain) (domB :: Domain) a . (HasCallStack, KnownNat nAddrs, KnownDomain domA, KnownDomain domB, NFDataX a) => Clock domA -> Clock domB -> Signal domA (RamOp nAddrs a) -> Signal domB (RamOp nAddrs a) -> (Signal domA a, Signal domB a)

    clash-prelude Clash.Explicit.Prelude.Safe

    Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.

  3. trueDualPortBlockRam :: forall (nAddrs :: Nat) (dom :: Domain) a . (HasCallStack, KnownNat nAddrs, HiddenClock dom, NFDataX a) => Signal dom (RamOp nAddrs a) -> Signal dom (RamOp nAddrs a) -> (Signal dom a, Signal dom a)

    clash-prelude Clash.Prelude

    Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.

  4. trueDualPortBlockRam :: forall (nAddrs :: Nat) (dom :: Domain) a . (HasCallStack, KnownNat nAddrs, HiddenClock dom, NFDataX a) => Signal dom (RamOp nAddrs a) -> Signal dom (RamOp nAddrs a) -> (Signal dom a, Signal dom a)

    clash-prelude Clash.Prelude.BlockRam

    Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.

  5. trueDualPortBlockRam :: forall (nAddrs :: Nat) (dom :: Domain) a . (HasCallStack, KnownNat nAddrs, HiddenClock dom, NFDataX a) => Signal dom (RamOp nAddrs a) -> Signal dom (RamOp nAddrs a) -> (Signal dom a, Signal dom a)

    clash-prelude Clash.Prelude.Safe

    Produces vendor-agnostic HDL that will be inferred as a true dual-port block RAM Any value that is being written on a particular port is also the value that will be read on that port, i.e. the same-port read/write behavior is: WriteFirst. For mixed-port read/write, when port A writes to the address port B reads from, the output of port B is undefined, and vice versa.

  6. encoderResidualPartitionOrders :: EncoderSettings -> !Maybe (Word32, Word32)

    flac Codec.Audio.FLAC.StreamEncoder

    Set the minimum and maximum partition order to search when coding the residual. The partition order determines the context size in the residual. The context size will be approximately blocksize / (2 ^ order). Set both min and max values to 0 to force a single context, whose Rice parameter is based on the residual signal variance. Otherwise, set a min and max order, and the encoder will search all orders, using the mean of each context for its Rice parameter, and use the best. Default: Nothing.

  7. glp_dual_rtest :: Ptr Problem -> CInt -> Ptr CInt -> Ptr CDouble -> CInt -> CDouble -> IO CInt

    glpk-headers Math.Programming.Glpk.Header

    No documentation available.

  8. glp_get_col_dual :: Ptr Problem -> Column -> IO CDouble

    glpk-headers Math.Programming.Glpk.Header

    No documentation available.

  9. glp_get_dual_stat :: Ptr Problem -> IO GlpkSolutionStatus

    glpk-headers Math.Programming.Glpk.Header

    No documentation available.

  10. glp_get_row_dual :: Ptr Problem -> Row -> IO CDouble

    glpk-headers Math.Programming.Glpk.Header

    No documentation available.

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