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1. readLn :: Read a => IO a

   clash-prelude	Clash.HaskellPrelude

   The readLn function combines getLine and readIO.

2. readParen :: Bool -> ReadS a -> ReadS a

   clash-prelude	Clash.HaskellPrelude

   readParen True p parses what p parses, but surrounded with parentheses. readParen False p parses what p parses, but optionally surrounded with parentheses.

3. reads :: Read a => ReadS a

   clash-prelude	Clash.HaskellPrelude

   equivalent to readsPrec with a precedence of 0.

4. readsPrec :: Read a => Int -> ReadS a

   clash-prelude	Clash.HaskellPrelude

   attempts to parse a value from the front of the string, returning a list of (parsed value, remaining string) pairs. If there is no successful parse, the returned list is empty. Derived instances of Read and Show satisfy the following:

   • (x,"") is an element of (readsPrec d (showsPrec d x "")).
   That is, readsPrec parses the string produced by showsPrec, and delivers the value that showsPrec started with.

5. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

   clash-prelude	Clash.Prelude

   Read the value from an inout port

6. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

   clash-prelude	Clash.Prelude

   Create a read-after-write block RAM from a read-before-write one

   >>> :t readNew (blockRam (0 :> 1 :> Nil))
   readNew (blockRam (0 :> 1 :> Nil))
   :: ...
   ...
   ... =>
   Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
   

   # 867 "srcClashPrelude/BlockRam.hs"

7. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

   clash-prelude	Clash.Prelude.BlockRam

   Create a read-after-write block RAM from a read-before-write one

   >>> :t readNew (blockRam (0 :> 1 :> Nil))
   readNew (blockRam (0 :> 1 :> Nil))
   :: ...
   ...
   ... =>
   Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
   

   # 867 "srcClashPrelude/BlockRam.hs"

8. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

   clash-prelude	Clash.Prelude.Safe

   Create a read-after-write block RAM from a read-before-write one

   >>> :t readNew (blockRam (0 :> 1 :> Nil))
   readNew (blockRam (0 :> 1 :> Nil))
   :: ...
   ...
   ... =>
   Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
   

   # 867 "srcClashPrelude/BlockRam.hs"

9. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

   clash-prelude	Clash.Signal

   Read the value from an inout port

10. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

    clash-prelude	Clash.Signal.BiSignal

    Read the value from an inout port

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