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  1. forceV :: forall (n :: Nat) a . KnownNat n => Vec n a -> Vec n a

    clash-prelude Clash.Prelude.Safe

    Evaluate all elements of a vector to WHNF

  2. forceVX :: forall (n :: Nat) a . KnownNat n => Vec n a -> Vec n a

    clash-prelude Clash.Prelude.Safe

    Evaluate all elements of a vector to WHNF. Does not propagate XExceptions.

  3. forward :: forall (d :: Nat) (dom :: Domain) (n :: Nat) a . SNat d -> DSignal dom n a -> DSignal dom (n + d) a

    clash-prelude Clash.Signal.Delayed

    EXPERIMENTAL Access a delayed signal from the past in the present. In contrast with delayed and friends forward does not insert any logic. This means using this function violates the delay invariant of DSignal. This is sometimes useful when combining unrelated delayed signals where inserting logic is not wanted or when abstracting over internal delayed signals where the internal delay information should not be leaked. For example, the circuit below returns a sequence of numbers as a pair but the internal delay information between the elements of the pair should not leak into the type.

    numbers
    :: forall dom
    . KnownDomain dom
    => Clock dom
    -> Reset dom
    -> Enable dom
    -> DSignal dom 5 (Int, Int)
    numbers clk rst en = DB.bundle (forward d1 s1, s2)
    where
    s1 :: DSignal dom 4 Int
    s1 = delayed clk rst en (100 :> 10 :> 5 :> 1 :> Nil) (pure 200)
    s2 :: DSignal dom 5 Int
    s2 = fmap (2*) $ delayN d1 0 en clk s1
    
    >>> sampleN 8 (toSignal (numbers systemClockGen systemResetGen enableGen))
    [(1,0),(1,2),(5,2),(10,10),(100,20),(200,200),(200,400),(200,400)]
    

  4. forward :: forall (d :: Nat) (dom :: Domain) (n :: Nat) a . SNat d -> DSignal dom n a -> DSignal dom (n + d) a

    clash-prelude Clash.Signal.Delayed.Internal

    EXPERIMENTAL Access a delayed signal from the past in the present. In contrast with delayed and friends forward does not insert any logic. This means using this function violates the delay invariant of DSignal. This is sometimes useful when combining unrelated delayed signals where inserting logic is not wanted or when abstracting over internal delayed signals where the internal delay information should not be leaked. For example, the circuit below returns a sequence of numbers as a pair but the internal delay information between the elements of the pair should not leak into the type.

    numbers
    :: forall dom
    . KnownDomain dom
    => Clock dom
    -> Reset dom
    -> Enable dom
    -> DSignal dom 5 (Int, Int)
    numbers clk rst en = DB.bundle (forward d1 s1, s2)
    where
    s1 :: DSignal dom 4 Int
    s1 = delayed clk rst en (100 :> 10 :> 5 :> 1 :> Nil) (pure 200)
    s2 :: DSignal dom 5 Int
    s2 = fmap (2*) $ delayN d1 0 en clk s1
    
    >>> sampleN 8 (toSignal (numbers systemClockGen systemResetGen enableGen))
    [(1,0),(1,2),(5,2),(10,10),(100,20),(200,200),(200,400),(200,400)]
    

  5. forceV :: forall (n :: Nat) a . KnownNat n => Vec n a -> Vec n a

    clash-prelude Clash.Sized.Vector

    Evaluate all elements of a vector to WHNF

  6. forceVX :: forall (n :: Nat) a . KnownNat n => Vec n a -> Vec n a

    clash-prelude Clash.Sized.Vector

    Evaluate all elements of a vector to WHNF. Does not propagate XExceptions.

  7. forceX :: NFDataX a => a -> a

    clash-prelude Clash.XException

    a variant of deepseqX that is useful in some circumstances:

    forceX x = x `deepseqX` x
    

  8. formatEvalHistogram :: Map Eval Int -> String

    combinatorial Combinatorics.Mastermind

    No documentation available.

  9. forConcurrently :: (Traversable t, MonadConc m) => t a -> (a -> m b) -> m (t b)

    concurrency Control.Concurrent.Classy.Async

    forConcurrently is mapConcurrently with its arguments flipped

    pages <- forConcurrently ["url1", "url2", "url3"] $ \url -> getURL url
    

  10. forConcurrently_ :: (Foldable f, MonadConc m) => f a -> (a -> m b) -> m ()

    concurrency Control.Concurrent.Classy.Async

    forConcurrently_ is forConcurrently with the return value discarded, just like forM_.

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