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clash-prelude Clash.Annotations.Primitive Warning that will be emitted on instantiating a guarded value.
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clash-prelude Clash.Annotations.TopEntity Give port names for arguments/results. Give a data type and function:
data T = MkT Int Bool {-# ANN f (defSyn "f") #-} f :: Int -> T -> (T,Bool) f a b = ...Clash would normally generate the following VHDL entity:entity f is port(a : in signed(63 downto 0); b_0 : in signed(63 downto 0); b_1 : in boolean; result : out std_logic_vector(65 downto 0)); end;
However, we can change this by using PortNames. So by:{-# ANN f (Synthesize { t_name = "f" , t_inputs = [ PortName "a" , PortName "b" ] , t_output = PortName "res" }) #-} f :: Int -> T -> (T,Bool) f a b = ...we get:entity f is port(a : in signed(63 downto 0); b : in std_logic_vector(64 downto 0); res : out std_logic_vector(65 downto 0)); end;
If we want to name fields for tuples/records we have to use PortProduct{-# ANN f (Synthesize { t_name = "f" , t_inputs = [ PortName "a" , PortProduct "" [ PortName "b", PortName "c" ] ] , t_output = PortProduct "res" [PortName "q"] }) #-} f :: Int -> T -> (T,Bool) f a b = ...So that we get:entity f is port(a : in signed(63 downto 0); b : in signed(63 downto 0); c : in boolean; res_q : out std_logic_vector(64 downto 0); res_1 : out boolean); end;
Notice how we didn't name the second field of the result, and the second output port got PortProduct name, "res", as a prefix for its name. PortName :: String -> PortNameclash-prelude Clash.Annotations.TopEntity You want a port, with the given name, for the entire argument/type You can use an empty String ,"" , in case you want an auto-generated name.
PortProduct :: String -> [PortName] -> PortNameclash-prelude Clash.Annotations.TopEntity You want to assign ports to fields of a product argument/type The first argument of PortProduct is the name of:
- The signal/wire to which the individual ports are aggregated.
- The prefix for any unnamed ports below the PortProduct
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No documentation available.
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clash-prelude Clash.Class.Parity Determine whether value is odd or even
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This module defines the explicitly clocked counterparts of the functions defined in Clash.Prelude.
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clash-prelude Clash.Explicit.Signal inout port behaves as if connected to a pull-down resistor
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clash-prelude Clash.Explicit.Signal inout port behaves as if connected to a pull-up resistor
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clash-prelude Clash.Explicit.Verification Property Specification Language