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  1. readsPrec :: Read a => Int -> ReadS a

    clash-prelude Clash.HaskellPrelude

    attempts to parse a value from the front of the string, returning a list of (parsed value, remaining string) pairs. If there is no successful parse, the returned list is empty. Derived instances of Read and Show satisfy the following:

    That is, readsPrec parses the string produced by showsPrec, and delivers the value that showsPrec started with.

  2. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

    clash-prelude Clash.Prelude

    Read the value from an inout port

  3. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Prelude

    Create a read-after-write block RAM from a read-before-write one 

    >>> :t readNew (blockRam (0 :> 1 :> Nil))
readNew (blockRam (0 :> 1 :> Nil))
:: ...
...
... =>
Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
    # 867 "srcClashPrelude/BlockRam.hs"

  4. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Prelude.BlockRam

    Create a read-after-write block RAM from a read-before-write one 

    >>> :t readNew (blockRam (0 :> 1 :> Nil))
readNew (blockRam (0 :> 1 :> Nil))
:: ...
...
... =>
Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
    # 867 "srcClashPrelude/BlockRam.hs"

  5. readNew :: forall (dom :: Domain) a addr . (HiddenClockResetEnable dom, NFDataX a, Eq addr) => (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Prelude.Safe

    Create a read-after-write block RAM from a read-before-write one 

    >>> :t readNew (blockRam (0 :> 1 :> Nil))
readNew (blockRam (0 :> 1 :> Nil))
:: ...
...
... =>
Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
    # 867 "srcClashPrelude/BlockRam.hs"

  6. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

    clash-prelude Clash.Signal

    Read the value from an inout port

  7. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

    clash-prelude Clash.Signal.BiSignal

    Read the value from an inout port

  8. readerC :: forall (m :: Type -> Type) r i o a . Monad m => (r -> ConduitT i o m a) -> ConduitT i o (ReaderT r m) a

    classy-prelude-conduit ClassyPrelude.Conduit

    Wrap the base monad in ReaderT Since 1.0.11

  9. readBoundedChan :: MonadConc m => BoundedChan m a -> m a

    concurrency Control.Concurrent.Classy.BoundedChan

    Read an element from the channel. If the channel is empty, this routine will block until it is able to read. Blockers wait in a fair FIFO queue.

  10. readCRef :: MonadConc m => CRef m a -> m a

    concurrency Control.Concurrent.Classy.CRef

    Read the current value stored in a reference.

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