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Within LTS Haskell 24.58 (ghc-9.10.3)

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  1. readCookie :: (Read a, MonadCGI m) => String -> m (Maybe a)

    cgi Network.CGI

    Same as getCookie, but tries to read the value to the desired type.

  2. readInput :: (Read a, MonadCGI m) => String -> m (Maybe a)

    cgi Network.CGI

    Same as getInput, but tries to read the value to the desired type.

  3. readCookies :: String -> [(String, String)]

    cgi Network.CGI.Cookie

    Gets all the cookies from a Cookie: header value

  4. readOnly :: forall (scope :: Scope) a . (ChanScoped c, Readable scope) => c scope a -> c 'Read a

    chan Control.Concurrent.Chan.Extra

    No documentation available.

  5. readChanRW :: forall (scope :: Scope) a . Readable scope => ChanRW scope a -> IO a

    chan Control.Concurrent.Chan.Typed

    No documentation available.

  6. readTChanRW :: forall (scope :: Scope) a . Readable scope => TChanRW scope a -> STM a

    chan Control.Concurrent.STM.TChan.Typed

    No documentation available.

  7. readNew :: forall (dom :: Domain) a addr . (KnownDomain dom, NFDataX a, Eq addr) => Clock dom -> Reset dom -> Enable dom -> (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Explicit.BlockRam

    Create a read-after-write block RAM from a read-before-write one

  8. readNew :: forall (dom :: Domain) a addr . (KnownDomain dom, NFDataX a, Eq addr) => Clock dom -> Reset dom -> Enable dom -> (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Explicit.Prelude

    Create a read-after-write block RAM from a read-before-write one

  9. readNew :: forall (dom :: Domain) a addr . (KnownDomain dom, NFDataX a, Eq addr) => Clock dom -> Reset dom -> Enable dom -> (Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a) -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a

    clash-prelude Clash.Explicit.Prelude.Safe

    Create a read-after-write block RAM from a read-before-write one

  10. readFromBiSignal :: forall a (ds :: BiSignalDefault) (d :: Domain) . (HasCallStack, BitPack a) => BiSignalIn ds d (BitSize a) -> Signal d a

    clash-prelude Clash.Explicit.Signal

    Read the value from an inout port

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