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1. stepcat :: [Pattern a] -> Pattern a

   tidal-core	Sound.Tidal.Stepwise

   No documentation available.

2. stepdrop :: Pattern Time -> Pattern a -> Pattern a

   tidal-core	Sound.Tidal.Stepwise

   No documentation available.

3. steptake :: Pattern Time -> Pattern a -> Pattern a

   tidal-core	Sound.Tidal.Stepwise

   No documentation available.

4. stepUpInterestInfo :: StepUp -> InterestInfo -> InterestInfo

   Hastructure	Liability

   get reset dates from interest info

5. stepX :: StateFDTD -> R

   LPFP	LPFP.Maxwell

   No documentation available.

6. stepY :: StateFDTD -> R

   LPFP	LPFP.Maxwell

   No documentation available.

7. stepZ :: StateFDTD -> R

   LPFP	LPFP.Maxwell

   No documentation available.

8. stepPhysics :: forall (m :: Type -> Type) w . (MonadIO m, Has w m Physics) => Double -> SystemT w m ()

   apecs-physics	Apecs.Physics

   No documentation available.

9. stepLock :: forall (dom :: Domain) . LockStep a b => DataFlow dom Bool a b b

   clash-prelude	Clash.Prelude.DataFlow

   Extend the synchronization granularity from a single Boolean value. Given:

   f :: DataFlow Bool Bool a b
   g :: DataFlow Bool Bool c d
   h :: DataFlow Bool Bool (p,q) (a,c)
   

   We cannot simply write:

   h `seqDF` (f `parDF` g)
   

   because, f `parDF` g, has type, DataFlow (Bool,Bool) (Bool,Bool) (a,c) (b,d), which does not match the expected synchronization granularity of h. We need a circuit in between that has the type:

   DataFlow Bool (Bool,Bool) (a,c) (a,c)
   

   Simply &&-ing the ready signals in the backward direction, and duplicating the valid signal in the forward direction is however not enough. We need to make sure that f does not consume values when g is not ready and visa versa, because h cannot update the values of its output tuple independently. f's valid port is hence only asserted when h is valid and g is ready to receive new values. g's valid port is only asserted when h is valid and f is ready to receive new values. f and g will hence be proceeding in lock-step. The stepLock function ensures that all synchronization signals are properly connected:

   h `seqDF` stepLock `seqDF` (f `parDF` g)
   

   Note 1: ensure that the components that you are synchronizing have buffered/delayed ready and valid signals, or stepLock has the potential to introduce combinational loops. You can do this by placing fifoDFs on the parallel channels. Extending the above example, you would write:

   h `seqDF` stepLock `seqDF` ((fifoDF d4 Nil `seqDF` f) `parDF` (fifoDF d4 Nil `seqDF` g))
   

   Note 2: stepLock works for arbitrarily nested tuples. That is:

   p :: DataFlow Bool Bool z ((a,c),c)
   
   q :: DataFlow ((Bool,Bool),Bool) ((Bool,Bool),Bool) ((a,c),c) ((b,d),d)
   q = f `parDF` g `parDF` g
   
   r = p `seqDF` stepLock `seqDF` q
   

   Does the right thing.

10. step_ :: Machine da db -> (Base da, da) -> (db, Machine da db)

    delta-types	Data.Delta.Embedding.Internal

    No documentation available.

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