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1. testFor :: Foldable f => Int -> f Bool -> Property

   clash-prelude	Clash.Explicit.Signal

   The above type is a generalization for:

   testFor :: Int -> Signal dom Bool -> Property
   

   testFor n s tests the signal s for n cycles. NB: This function is not synthesizable

2. ignoreFor :: forall (dom :: Domain) (n :: Nat) a . KnownDomain dom => Clock dom -> Reset dom -> Enable dom -> SNat n -> a -> Signal dom a -> Signal dom a

   clash-prelude	Clash.Explicit.Testbench

   Ignore signal for a number of cycles, while outputting a static value.

3. YosysFormal :: RenderAs

   clash-prelude	Clash.Explicit.Verification

   Yosys Formal Extensions for Verilog and SystemVerilog. See: https://symbiyosys.readthedocs.io/en/latest/verilog.html and https://symbiyosys.readthedocs.io/en/latest/verific.html Falls back to PSL for VHDL, however currently Clash's PSL syntax isn't suported by GHDL+SymbiYosys;

4. before :: forall (dom :: Domain) a b . (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom

   clash-prelude	Clash.Explicit.Verification

   Same as a && next b but with a nice syntax. E.g., a && next b could be written as a `before` b. Might be read as "a happens one cycle before b".

5. testFor :: forall (dom :: Domain) . KnownDomain dom => Int -> (HiddenClockResetEnable dom => Signal dom Bool) -> Property

   clash-prelude	Clash.Prelude

   testFor n s tests the signal s for n cycles. NB: This function is not synthesizable

6. ignoreFor :: forall (dom :: Domain) (n :: Nat) a . HiddenClockResetEnable dom => SNat n -> a -> Signal dom a -> Signal dom a

   clash-prelude	Clash.Prelude.Testbench

   Ignore signal for a number of cycles, while outputting a static value.

7. testFor :: forall (dom :: Domain) . KnownDomain dom => Int -> (HiddenClockResetEnable dom => Signal dom Bool) -> Property

   clash-prelude	Clash.Signal

   testFor n s tests the signal s for n cycles. NB: This function is not synthesizable

8. testFor :: Foldable f => Int -> f Bool -> Property

   clash-prelude	Clash.Signal.Internal

   The above type is a generalization for:

   testFor :: Int -> Signal dom Bool -> Property
   

   testFor n s tests the signal s for n cycles. NB: This function is not synthesizable

9. waitForTraces# :: forall a (dom :: Domain) . NFDataX a => IORef TraceMap -> Signal dom a -> [String] -> IO ()

   clash-prelude	Clash.Signal.Trace

   Keep evaluating given signal until all trace names are present.

10. YosysFormal :: RenderAs

    clash-prelude	Clash.Verification

    Yosys Formal Extensions for Verilog and SystemVerilog. See: https://symbiyosys.readthedocs.io/en/latest/verilog.html and https://symbiyosys.readthedocs.io/en/latest/verific.html Falls back to PSL for VHDL, however currently Clash's PSL syntax isn't suported by GHDL+SymbiYosys;

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