Deprecated

In favour of
clash-lib

clash-verilog

CAES Language for Synchronous Hardware - Verilog backend

http://www.clash-lang.org/

Version on this page:0.5.7
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-verilog appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-verilog-0.5.7@sha256:e53cdfe2d11a16cf5db5cb3e37f834f6bd6e543e0830faddf49760955b09d422,3726

Module documentation for 0.5.7

Used by 1 package in lts-3.0(full list with versions):
clash-ghc

Support

For updates and questions join the mailing list [email protected] or read the forum

clash-verilog

  • See the LICENSE file for license and copyright details

Changes

Changelog for the clash-systemverilog package

0.5.7 June 26th 2015

  • New features:
    • Generate Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus

0.5.6 June 25th 2015

  • New features:

    • Support clash-prelude-0.9

  • Fixes bug:

    • Can not operate “shiftR” on Int #63
    • Fail to generate verilog when using “quot” and “div” on Index #64

0.5.5 June 3rd 2015

  • Initial release