clash-systemverilog

CAES Language for Synchronous Hardware - SystemVerilog backend http://www.clash-lang.org/

Version on this page:0.5.10
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-systemverilog appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij

Module documentation for 0.5.10

This version can be pinned in stack with:[email protected]:72217e7d23a46ac16e68f742a5ef7dd2835cd1e645885286f14d1108ff07395c,4448

clash-systemverilog - SystemVerilog backend for the CλaSH compiler

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, which enables both safe and fast prototying using consise descriptions (like Verilog)

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list [email protected] or read the forum

Changes

Changelog for the clash-systemverilog package

0.5.10 September 21st 2015

  • New features:
    • Report simulation time in assert messages

0.5.9 September 14 2015

  • Support for clash-lib-0.5.12

0.5.8 September 7th 2015

  • Fixes bugs:
    • Fix primitive for CLaSH.Sized.Internal.Signed.size# #72
    • rem and quot on Signed are broken #73

0.5.7 June 26th 2015

  • Fixes bug:
    • Incorrect primitive for CLaSH.Prelude.Testbench.assert'
    • Incorrect primitive for CLaSH.Sized.Vec.index_int
    • Sometimes created incorrect nested generate statements

0.5.6 June 25th 2015

  • New features:

    • Support clash-prelude-0.9
  • Fixes bug:

    • Can not operate “shiftR” on Int #63
    • Fail to generate verilog when using “quot” and “div” on Index #64

0.5.5 June 3rd 2015

  • New features:
    • Compile against clash-lib-0.5.6
    • Generated component names are prefixed by the name of the module containing the topEntity

0.5.4 May 10th 2015

  • New features:
    • Generate smarter labels for register and blockRam blackboxes to make finding longest paths easier

0.5.3 May 5th 2015

  • Fixes bugs:
    • Incorrect implementation of rotateL and rotateR blackbox for BitVector

0.5.2 May 1st 2015

  • New features:
    • Support wrapper generation

0.5.1 April 20th 2015

  • Update to clash-prelude 0.7.2

0.5 March 11th 2015

  • Initial release