Deprecated
clash-vhdl
CAES Language for Synchronous Hardware - VHDL backend
Version on this page: | 0.6.16@rev:1 |
LTS Haskell 9.21: | 0.7.2 |
Stackage Nightly 2017-07-25: | 0.7.2 |
Latest on Hackage: | 0.7.2 |
clash-vhdl-0.6.16@sha256:b2816898222a54367e8426adb2f3359fd32b1ec8e00d546f32ff3f2839c01b3c,4937
Module documentation for 0.6.16
- CLaSH
- CLaSH.Backend
clash-vhdl
- VHDL backend for the CλaSH compiler
- See the LICENSE file for license and copyright details
CλaSH - A functional hardware description language
CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
-
Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).
-
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
-
Higher-order functions, with type inference, result in designs that are fully parametric by default.
-
Synchronous sequential circuit design based on streams of values, called
Signal
s, lead to natural descriptions of feedback loops. -
Support for multiple clock domains, with type safe clock domain crossing.
Support
For updates and questions join the mailing list [email protected] or read the forum
Changes
Changelog for the clash-vhdl
package
0.6.16
- Fixes bugs:
- Incorrect primitive for
Integer
sltInteger#
andgeInteger#
- Incorrect primitive for
0.6.15 July 19th 2016
- Fixes bugs:
- Incorrect primitive for
Index
s*#
- Incorrect handling of
Index
sfromInteger#
andmaxBound#
primitives for values larger than 2^MACHINE_WIDTH
- Incorrect primitive for
0.6.14 July 15th 2016
- New features:
- Support clash-lib-0.6.18
- Fixes bugs:
- Incorrect primitive specifications for Integer’s
shiftL
andshiftR
- Types in generated types.vhdl incorrectly sorted
- Incorrect primitive specifications for Integer’s
0.6.13 June 9th 2016
- Fixes bugs:
- Converting product types to std_logic_vector fails when the
clash-hdlsyn Vivado
flag is enabled
- Converting product types to std_logic_vector fails when the
0.6.12 June 7th 2016
- Fixes bugs:
- Incorrect primitive specification for
snatToInteger
#149
- Incorrect primitive specification for
0.6.11 April 7th 2016
- Fixes bugs:
- Incorrect primitives for
BitVector
squot#
andrem#
- Bit indexing and replacement primitives fail to synthesise in Synopsis tools
- Incorrect primitives for
0.6.10 March 15th 2016
- Fixes bugs:
- XST cannot finds “_types” package unless it is prefixed with “work.” #133
0.6.9 March 15th 2016
- Fixes bugs:
- XST cannot finds “_types” package unless it is prefixed with “work.” #133
0.6.8 March 11th 2016
- Support
clash-lib
0.6.11 - Fixes bugs:
- Vivado fails to infer block ram #127
- Users must use the
-clash-hdlsyn Vivado
flag in order to generate Xilinx Vivado specific HDL for which Vivado can infer block RAM.
- Users must use the
- Vivado fails to infer block ram #127
0.6.7 February 10th 2016
- Fixes bugs:
- insufficient type-qualifiers for concatenation operator #121
0.6.6 January 29th 2016
- New features:
- Support clash-lib-0.6.9
- Support for
Debug.Trace.trace
, thanks to @ggreif
- Fixes bugs:
- BlockRAM elements must be bit vectors #113
0.6.5 January 13th 2016
- New features:
- Support for Haskell’s:
Char
,Int8
,Int16
,Int32
,Int64
,Word
,Word8
,Word16
,Word32
,Word64
. - Int/Word/Integer bitwidth for generated VHDL is configurable using the
-clash-intwidth=N
flag, whereN
can be either 32 or 64.
- Support for Haskell’s:
0.6.4 November 17th 2015
- Fixes bugs:
- Integer literals should only be capped to 32-bit when used in assignments.
0.6.3 November 12th 2015
- Fixes bugs:
- Do not generate overlapping literal patterns #91
0.6.2 October 21st 2015
- New features:
- Support
clash-prelude
0.10.2
- Support
0.6.1 October 16th 2015
- New features:
- Support for
clash-prelude
0.10.1
- Support for
0.6 October 3rd 2015
- New features:
- Support
clash-prelude-0.10
- Support
0.5.12 September 21st 2015
- Fixes bugs:
- Fix Index maxBound #79
0.5.11 September 14th 2015
- Support for clash-lib-0.5.12
- Fixes bugs:
- Converting Bool to Unsigned generates broken VHDL #77
0.5.10 September 8th 2015
- Fixes bugs:
- Maybe (Index n) not translatable to VHDL #75
0.5.9 September 7th 2015
- Fixes bugs:
0.5.8 July 9th 2015
- New features:
- Generate VHDL-93 instead of VHDL-2002, the VHDL-93 standard is supported by a larger range of tools
0.5.7.1 June 26th 2015
- Support for
genStmt
backend method
0.5.7 June 25th 2015
-
New features:
- Support
clash-prelude-0.9
- Support
-
Fixes bug:
0.5.6 June 5th 2015
- Fixes bugs:
- Incorrect extraction of
Bool
value out of a Sum-of-Product type
- Incorrect extraction of
0.5.5 June 3rd 2015
- New features:
- Compile against
clash-lib-0.5.6
- Generated component names are prefixed by the name of the module containing the
topEntity
- Compile against
0.5.4 May 10th 2015
-
New features:
- Make VHDL ‘assert’ primitive GHDL friendly
- Generate smarter labels for
register
andblockRam
blackboxes to make finding longest paths easier
-
Fixes bugs:
- Incorrect primitives for BitVector
minBound
andmaxBound
- Incorrect primitives for BitVector
0.5.3 May 1st 2015
-
New features:
- Support wrapper generation
-
Fixes bugs:
- Incorrect primitives for BitVector
minBound
andmaxBound
- Incorrect primitives for BitVector
0.5.2 April 24th 2015
- Fixes bugs:
- Fix bug where not enough array type definitions were created
0.5.1 April 20th 2015
- Update to clash-prelude 0.7.2
0.5 March 11th 2015
- Initial release