Deprecated

In favour of
clash-lib

clash-systemverilog

CAES Language for Synchronous Hardware - SystemVerilog backend

http://www.clash-lang.org/

Version on this page:0.5.4
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-systemverilog appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-systemverilog-0.5.4@sha256:4a3562822d88a6f0656e15dd24960ac49e5c0fd29f60019ecbac7beb2a4155ef,3519

Module documentation for 0.5.4

Used by 1 package in nightly-2015-05-13(full list with versions):
clash-ghc

Support

For updates and questions join the mailing list [email protected] or read the forum

clash-systemverilog

  • See the LICENSE file for license and copyright details

Changes

Changelog for the clash-systemverilog package

0.5.4

  • New features:
    • Generate smarter labels for register and blockRam blackboxes to make finding longest paths easier

0.5.3 May 5th 2015

  • Fixes bugs:
    • Incorrect implementation of rotateL and rotateR blackbox for BitVector

0.5.2 May 1st 2015

  • New features:
    • Support wrapper generation

0.5.1 April 20th 2015

  • Update to clash-prelude 0.7.2

0.5 March 11th 2015

  • Initial release