Deprecated

In favour of

clash-vhdl

CAES Language for Synchronous Hardware - VHDL backend

http://www.clash-lang.org/

Version on this page:0.5.4
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-vhdl appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-vhdl-0.5.4@sha256:7c3184612898769caf185eb2a239d0746380c8daa4468afac5608142b6b87af1,3474

Module documentation for 0.5.4

Support

For updates and questions join the mailing list [email protected] or read the forum

clash-vhdl

  • See the LICENSE file for license and copyright details

Changes

Changelog for the clash-vhdl package

0.5.4

  • New features:

    • Make VHDL ‘assert’ primitive GHDL friendly
    • Generate smarter labels for register and blockRam blackboxes to make finding longest paths easier
  • Fixes bugs:

    • Incorrect primitives for BitVector minBound and maxBound

0.5.3 May 1st 2015

  • New features:

    • Support wrapper generation
  • Fixes bugs:

    • Incorrect primitives for BitVector minBound and maxBound

0.5.2 April 24th 2015

  • Fixes bugs:
    • Fix bug where not enough array type definitions were created

0.5.1 April 20th 2015

  • Update to clash-prelude 0.7.2

0.5 March 11th 2015

  • Initial release