Deprecated

In favour of
clash-lib

clash-systemverilog

CAES Language for Synchronous Hardware - SystemVerilog backend

http://www.clash-lang.org/

Version on this page:0.5.5
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-systemverilog appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-systemverilog-0.5.5@sha256:9dbbe26ac764da207eb4af0d34f5e44d105e186e67f8dad8ed5bb1b132d075b2,3517

Module documentation for 0.5.5

Used by 1 package in nightly-2015-06-16(full list with versions):
clash-ghc

Support

For updates and questions join the mailing list [email protected] or read the forum

clash-systemverilog

  • See the LICENSE file for license and copyright details

Changes

Changelog for the clash-systemverilog package

0.5.5 June 3rd 2015

  • New features:
    • Compile against clash-lib-0.5.6
    • Generated component names are prefixed by the name of the module containing the topEntity

0.5.4 May 10th 2015

  • New features:
    • Generate smarter labels for register and blockRam blackboxes to make finding longest paths easier

0.5.3 May 5th 2015

  • Fixes bugs:
    • Incorrect implementation of rotateL and rotateR blackbox for BitVector

0.5.2 May 1st 2015

  • New features:
    • Support wrapper generation

0.5.1 April 20th 2015

  • Update to clash-prelude 0.7.2

0.5 March 11th 2015

  • Initial release