BSD-2-Clause licensed by Christiaan Baaij
This version can be pinned in stack with:clash-systemverilog-0.5.7@sha256:8d7211a1fb8d514e7e52806960f9f0595442b5cf741da3ef60f88dcdc9b8671a,3756
Module documentation for 0.5.7
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clash-systemverilog
- See the LICENSE file for license and copyright details
0.5.7 June 26th 2015
- Fixes bug:
- Incorrect primitive for
CLaSH.Prelude.Testbench.assert'
- Incorrect primitive for
CLaSH.Sized.Vec.index_int
- Sometimes created incorrect nested
generate
statements
0.5.6 June 25th 2015
-
New features:
- Support
clash-prelude-0.9
-
Fixes bug:
- Can not operate “shiftR” on Int #63
- Fail to generate verilog when using “quot” and “div” on Index #64
0.5.5 June 3rd 2015
- New features:
- Compile against
clash-lib-0.5.6
- Generated component names are prefixed by the name of the module containing the
topEntity
0.5.4 May 10th 2015
- New features:
- Generate smarter labels for
register
and blockRam
blackboxes to make finding longest paths easier
0.5.3 May 5th 2015
- Fixes bugs:
- Incorrect implementation of rotateL and rotateR blackbox for BitVector
0.5.2 May 1st 2015
- New features:
- Support wrapper generation
0.5.1 April 20th 2015
- Update to clash-prelude 0.7.2
0.5 March 11th 2015