Deprecated

In favour of

clash-verilog

CAES Language for Synchronous Hardware - Verilog backend

http://www.clash-lang.org/

Version on this page:0.6
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-verilog appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-verilog-0.6@sha256:da5fd3cdc7369536667915f93cab8a56e7c61b5e48a59dbaf6df79cdb089b586,4457

Module documentation for 0.6

clash-verilog - Verilog backend for the CλaSH compiler

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list [email protected] or read the forum

Changes

Changelog for the clash-systemverilog package

0.6

  • New features:
    • Support clash-prelude-0.10

0.5.10 September 21st 2015

  • New features:
    • Report simulation time in assert messages

0.5.9 September 14th 2015

  • Support for clash-lib-0.5.12

0.5.8 September 7th 2015

  • Fixes bugs:
    • Fix primitive for CLaSH.Sized.Internal.Signed.size# #72
    • rem and quot on Signed are broken #73

0.5.7 June 26th 2015

  • New features:
    • Generate Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus

0.5.6 June 25th 2015

  • New features:

    • Support clash-prelude-0.9
  • Fixes bug:

    • Can not operate “shiftR” on Int #63
    • Fail to generate verilog when using “quot” and “div” on Index #64

0.5.5 June 3rd 2015

  • Initial release