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CAES Language for Synchronous Hardware - VHDL backend

Version on this page:0.6
LTS Haskell 9.21:0.7.2
Stackage Nightly 2017-07-25:0.7.2
Latest on Hackage:0.7.2

See all snapshots clash-vhdl appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-vhdl-0.6@sha256:1d90ecfea10f8615fc261389f054be4dc38ea2bb0063d627560902c5fb476bec,4442

Module documentation for 0.6

clash-vhdl - VHDL backend for the CλaSH compiler

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.


For updates and questions join the mailing list [email protected] or read the forum


Changelog for the clash-vhdl package

0.6 October 3rd 2015

  • New features:
    • Support clash-prelude-0.10

0.5.12 September 21st 2015

  • Fixes bugs:
    • Fix Index maxBound #79

0.5.11 September 14th 2015

  • Support for clash-lib-0.5.12
  • Fixes bugs:
    • Converting Bool to Unsigned generates broken VHDL #77

0.5.10 September 8th 2015

  • Fixes bugs:
    • Maybe (Index n) not translatable to VHDL #75

0.5.9 September 7th 2015

  • Fixes bugs:
    • Bug in VHDL ROM generation #69
    • Fix asyncRom VHDL primitive #71
    • Fix primitive for CLaSH.Sized.Internal.Signed.size# #72
    • rem and quot on Signed are broken #73

0.5.8 July 9th 2015

  • New features:
    • Generate VHDL-93 instead of VHDL-2002, the VHDL-93 standard is supported by a larger range of tools June 26th 2015

  • Support for genStmt backend method

0.5.7 June 25th 2015

  • New features:

    • Support clash-prelude-0.9
  • Fixes bug:

    • Can not operate “shiftR” on Int #63
    • Fail to generate verilog when using “quot” and “div” on Index #64

0.5.6 June 5th 2015

  • Fixes bugs:
    • Incorrect extraction of Bool value out of a Sum-of-Product type

0.5.5 June 3rd 2015

  • New features:
    • Compile against clash-lib-0.5.6
    • Generated component names are prefixed by the name of the module containing the topEntity

0.5.4 May 10th 2015

  • New features:

    • Make VHDL ‘assert’ primitive GHDL friendly
    • Generate smarter labels for register and blockRam blackboxes to make finding longest paths easier
  • Fixes bugs:

    • Incorrect primitives for BitVector minBound and maxBound

0.5.3 May 1st 2015

  • New features:

    • Support wrapper generation
  • Fixes bugs:

    • Incorrect primitives for BitVector minBound and maxBound

0.5.2 April 24th 2015

  • Fixes bugs:
    • Fix bug where not enough array type definitions were created

0.5.1 April 20th 2015

  • Update to clash-prelude 0.7.2

0.5 March 11th 2015

  • Initial release