Clash - A functional hardware description language
Clash is a functional hardware description language that borrows both
its syntax and semantics from the functional programming language
Haskell. The Clash compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
Strongly typed, yet with a very high degree of type inference, enabling both
safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are
fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.
Support for multiple clock domains, with type safe clock domain crossing.
The normalizeType function now fully normalizes types which require calls to
reduceTypeFamily #1469
flogBaseSNat, clogBaseSNat and logBaseSNat primitives are now implemented correctly.Previously these primitives would be left unevaluated causing issues as demonstrated in #1479
Specializing on functions with type family arguments no longer fails #1477
satSucc, satPred correctly handle “small types” such as Index 1.
msb no longer fails on values larger than 64 bits
undefined can now be used as a reset value of autoReg@Maybe#1507
Signal’s fmap is now less strict, preventing infinite loops in very specific situations. See #1521
Clash now uses correct function names in manifest and sdc files #1533
Clash no longer produces erroneous HDL in very specific cases #1536
Usage of fold inside other HO primitives (e.g., map) no longer fails #1524
1.2.4 July 28th 2020
Changed:
Relaxed upper bound versions of aeson and dlist, in preparation for the new Stack LTS.
Reverted changes to primitive definitions for ‘zipWith’, ‘map’, ‘foldr’, and ‘init’ introduced in 1.2.2. They have shown to cause problems in very specific circumstances.
1.2.3 July 11th 2020
Changed:
Upgrade to nixos 20.03. Nix and snap users will now use packages present in 20.03.
Added:
instance Monoid a => Monoid (Vec n a)
instance Text.Printf(Index)
instance Text.Printf(Signed)
instance Text.Printf(Unsigned)
Fixed:
Clash renders incorrect VHDL when GHCs Worker/Wrapper transformation is enabled #1402
Minor faults in generated HDL when using annotations from Clash.Annotations.SynthesisAttributes
The hardwired functions to unroll primitive definitions for ‘zipWith’, ‘map’, ‘foldr’, and ‘init’ have been changed to only unroll a single step, whereas they would previously unroll the whole definition in one step. This allows Clash to take advantage of the lazy nature of these functions, in turn speeding up compilation speeds significantly in some cases. Part of PR 1354.
Added:
Support for GHC 8.10
Ability to load designs from precompiled modules (i.e., stored in a package database). See #1172
Support for ‘-main-is’ when used with --vhdl, --verilog, or --systemverilog
Fix result type of head and tail Verilog blackboxes #1351
Certain recursive let-expressions in side a alternatives of a case-expression throw the Clash compiler into an infinite loop #1316
Fixes issue with one of Clash’s transformations, inlineCleanup, introducing free variables #1337
Fails to propagate type information of existential type #1310
Certain case-expressions throw the Clash compiler into an infinite loop #1320
Added blackbox implementation for ‘Clash.Sized.Vector.iterateI’, hence making it usable as a register reset value #1240
iterate and iterateI can now be used in reset values #1240
Prim evaluation fails on undefined arguments #1297
Missing re-indexing in (Un)Signed fromSLV conversion #1292
VHDL: generate a type qualification inside ~TOBV, fixes #1360
1.2.1 April 23rd 2020
Changed:
Treat Signed 0, Unsigned 0, Index 1, BitVector 0 as unit. In effect this means that ‘minBound’ and ‘maxBound’ return 0, whereas previously they might crash #1183
Infix use of deepseqX is now right-associative
Added:
Add ‘natToInteger’, ‘natToNatural’, and ‘natToNum’. Similar to ‘snatTo*’, but works solely on a type argument instead of an SNat.
Clash.Sized.Vector.unfoldr and Clash.Sized.Vector.unfoldrI to construct vectors from a seed value
Added NFDataX instances for Data.Monoid.{First,Last}
Fixed:
The Verilog backend can now deal with non-contiguous ranges in custom bit-representations.
Synthesizing BitPack instances for type with phantom parameter fails #1242
Synthesis of fromBNat (toBNat d5) failed due to unsafeCoerce coercing from Any
As promised when releasing 1.0, we’ve tried our best to keep the API stable. We
think most designs will continue to compile with this new version, although special
care needs to be taken when using:
Use inline blackboxes. Instead of taking a single HDL, inline primitives now
take multiple. For example, InlinePrimitive VHDL ".." must now be written
as InlinePrimitive [VHDL] "..".
Use the Enum instance for BitVector, Index, Signed, or Unsigned, as
they now respect their maxBound. See #1089.
On top of that, we’ve added a number of new features:
makeTopEntity: Template Haskell function for generating TopEntity annotations. See the documentation on Haddock for more information.
Clash.Explicit.SimIO: ((System)Verilog only) I/O actions that can be translated to HDL I/O. See the documentation on Haddock for more information.
Clash.Class.AutoReg: A smart register that improves the chances of synthesis tools inferring clock-gated registers, when used. See the documentation on Haddock for more information.
The full list of changes follows. Happy hacking!
New features (API):
Clash.Class.Parity type class replaces Prelude odd and even functions due to assumptions that don’t hold for Clash specific numerical types, see #970.
makeTopEntity Template Haskell function for generating TopEntity annotations
intended to cover the majority of use cases. Generation failures should either
result in an explicit error, or a valid annotation of an empty PortProduct.
Any discrepancy between the shape of generated annotations and the shape
of the Clash compiler is a bug. See #795.
Known limitations:
Type application (excluding Signals and :::) is best effort:
Data types with type parameters will work if the generator can discover a single relevant constructor after attempting type application.
Arbitrary explicit clock/reset/enables are supported, but only a single HiddenClockResetEnable constraint is supported.
Data/type family support is best effort.
Added Bundle ((f :*: g) a) instance
Added NFDataX CUShort instance
Clash’s internal type family solver now recognizes AppendSymbol and CmpSymbol
Added Clash.Magic.suffixNameFromNat: can be used in cases where suffixName is too slow
Added Clash.Class.AutoReg. Improves the chances of synthesis tools inferring clock-gated registers, when used. See #873.
Clash.Magic.suffixNameP, Clash.Magic.suffixNameFromNatP: enable prefixing of name suffixes
Added Clash.Magic.noDeDup: can be used to instruct Clash to /not/ share a function between multiple branches
A BitPack a constraint now implies a KnownNat (BitSize a) constraint, so you won’t have to add it manually anymore. See #942.
Clash.Explicit.SimIO: ((System)Verilog only) I/O actions that can be translated to HDL I/O; useful for generated test benches.
#439: Template Haskell splices and TopEntity annotations can now be used in clashi
#662: Clash will now constant specialize partially constant constructs
#700: Check work content of expression in cast before warning users. Should eliminate a lot of (superfluous) warnings about “specializing on non work-free cast”s.
#837: Blackboxes will now report clearer error messages if they’re given unexpected arguments.
#869: PLL is no longer duplicated in Blinker.hs example
#749: Clash’s dependencies now all work with GHC 8.8, allowing clash-{prelude,lib,ghc} to be compiled from Hackage soon.
API changes: check the migration guide at the end of Clash.Tutorial
All memory elements now have an (implicit) enable line; “Gated” clocks have been removed as the clock wasn’t actually gated, but implemented as an enable line.
Circuit domains are now configurable in:
(old) The clock period
(new) Clock edge on which memory elements latch their inputs (rising edge or falling edge)
(new) Whether the reset port of a memory element is level sensitive asynchronous reset) or edge sensitive (synchronous reset)
(new) Whether the reset port of a memory element is active-high or active-low (negated reset)
(new) Whether memory element power on in a configurable/defined state (common on FPGAs) or in an undefined state (ASICs)
Experimental: Multiple hidden clocks. Can be enabled by compiling
clash-prelude with -fmultiple-hidden
Experimental: Limited GADT support (pattern matching on vectors, or custom
GADTs as longs as their usage can be statically removed; no support of
recursive GADTs)
InlinePrimitive support: specify HDL primitives inline with Haskell code
Support for ghc-typelits-natnormalise-0.6.1
Lift instances for TopEntity and PortName
InlinePrimitive support: specify HDL primitives inline with Haskell code
0.99 March 31st 2018
New features:
Major API overhaul: check the migration guide at the end of Clash.Tutorial
New features:
Explicit clock and reset arguments
Rename CLaSH to Clash
Implicit/Hidden clock and reset arguments using a combination of
reflection and ImplicitParams.
Large overhaul of TopEntity annotations
PLL and other clock sources can now be instantiated using regular functions:
Clash.Intel.ClockGen and Clash.Xilinx.ClockGen.
DDR registers:
Generic/ASIC: Clash.Explicit.DDR
Intel: Clash.Intel.DDR
Xilinx: Clash.Intel.Xilinx
Bit is now a newtype instead of a type synonym and will be mapped to
a HDL scalar instead of an array of one (e.g std_logic instead of
std_logic_vector(0 downto 0))
Hierarchies with multiple synthesisable boundaries by allowing more than one
function in scope to have a Synthesize annotation.
Local caching of functions with a Synthesize annotation
Bit type is mapped to a HDL scalar type (e.g. std_logic in VHDL)
Improved name preservation
Zero-bit values are filtered out of the generated HDL
