CAES Language for Synchronous Hardware

Version on this page:0.5.15@rev:1
LTS Haskell 19.33:1.6.4
Stackage Nightly 2024-07-13:1.8.1@rev:3
Latest on Hackage:1.8.1@rev:3

See all snapshots clash-ghc appears in

BSD-2-Clause licensed by Christiaan Baaij
Maintained by Christiaan Baaij
This version can be pinned in stack with:clash-ghc-0.5.15@sha256:2e620f3c94f1bd3039f7e8cbdd5f3f547182b4a657fcb2a5d05554d378b2ae6b,4808

Module documentation for 0.5.15

There are no documented modules for this package.

clash-ghc - Haskell/GHC front-end for the CλaSH compiler

  • See the LICENSE file for license and copyright details
  • Contains code from the GHC compiler, see the LICENSE_GHC file for license and copyright details pertaining to that code.

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, which enables both safe and fast prototying using consise descriptions (like Verilog)

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals.

  • Support for multiple clock domains, with type safe clock domain crossing.


For updates and questions join the mailing list [email protected] or read the forum


Changelog for the clash-ghc package

0.5.15 September 21st 2015

  • New features:

    • Report simulation time in (System)Verilog assert messages
  • Fixes bugs:

    • Performance bug: top-level definitions of type “Signal” erroneously inlined.
    • Fix Index maxBound #79

0.5.14 September 14th 2015

  • New features:

    • Completely unroll “definitions” of some higher-order primitives with non-representable argument or result vectors: It is now possible to translate e.g. f xs ys = zipWith ($) (map (+) xs) ys :: Vec 4 Int -> Vec 4 Int -> Vec 4 Int
  • Fixes bugs:

    • Converting Bool to Unsigned generates broken VHDL #77
    • topLet transformation erroneously not performed in a top-down traversal
    • Specialisation limit unchecked on types and constants
    • Vector of functions cannot be translated #25
    • CLaSH fails to generate VHDL when map is applied #78

0.5.13 September 8th 2015

  • Fixes bugs:
    • Cannot translate GHC MachLabel literal
    • Maybe (Index n) not translatable to VHDL #75

0.5.12 September 7th 2015

  • New features:

    • Modest compilation time speed-up. Compilation time of the I2C module on my machine went down from 43s to 24s, and maximum memory usage went down from 840 MB to 700 MB.
  • Fixes bugs:

    • Bug in VHDL ROM generation #69
    • Clash running out of memory on Simple-ish project #70
    • Fix asyncRom VHDL primitive #71
    • Fix primitive for CLaSH.Sized.Internal.Signed.size# #72
    • rem and quot on Signed are broken #73

0.5.11 August 2nd 2015

  • New features:
    • Re-enable GHC’s strictness analysis pass, which improves dead-code removal, which hopefully leads to smaller circuits.

0.5.10 July 9th 2015

  • New features:
    • Use new VHDL backend which outputs VHDL-93 instead of VHDL-2002: generated VHDL is now accepted by a larger number of tools.
    • Treat all so-called bottom values (error "FOO", let x = x in x, etc.) occuring in installed libraries as undefined. Before, there were (very) rare situations where we couldn’t find the expressions belonging to a function and demanded a BlackBox, even though we knew the expression would be a bottom value. Now, we stop demanding a BlackBox for such a function and simply treat it as undefined, thus allowing a greater range of circuit descriptions that we can compile.

0.5.9 June 26th 2015

  • New features:

    • Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
  • Fixes bugs:

    • --systemverilog switch incorrectly generates verilog code instead of systemverilog code

0.5.8 June 25th 2015

  • New features:
    • Support for copying string literals from Haskell to generated code
    • Support clash-prelude-0.9
    • Size at below which functions are always inlined is configurable, run with -clash-inline-below=N to set the size limit to N

0.5.7 June 3rd 2015

  • New features:
    • New Verilog backend, run :verilog in interactive mode, or --verilog for batch mode
    • Generated component names are prefixed by the name of the module containing the topEntity

0.5.6 May 18th 2015

  • New features:

    • Inlining limit is configurable, run with -clash-inline-limit=N to set the inlining limit to N
    • Specialisation limit is configurable, run with clash-spec-limit=N to set the inline limit to N
    • Debug level is configurable, run with -clash-debug <LEVEL> where <LEVEL> can be: DebugNone, DebugFinal, DebugName, DebugApplied, DebugAll. Be default, clash runs with DebugNone.
  • Fixes bugs:

    • Extend evaluator for GHC.Integer.Type.minusInteger and CLaSH.Promoted.Nat.SNat.

0.5.5 May 5th 2015

  • New features:
    • TopEntity wrappers are now specified as ANN annotation pragmas #42

0.5.4 May 1st 2015

  • New features:
    • Generate wrappers around topEntity that have constant names and types

0.5.3 April 24th 2015

  • Fixes bugs:
    • Fix bug where not enough array type definitions were created by the VHDL backend

0.5.2 April 21st 2015

  • Use latest ghc-typelits-natnormalise

0.5.1 April 20th 2015

0.5 March 11th 2015

  • New features:
    • SystemVerilog backend. #45

0.4.1 February 4th 2015

  • Include bug fixes from clash-lib 0.4.1

0.4 November 17th 2014

  • New features:

    • Support for clash-prelude 0.6
  • Fixes bugs:

    • clash-ghc ignores “-package-db” flag #35

0.3.3 August 12th 2014

  • Fixes bugs:
    • Compile with GHC 7.8.3 #31

0.3.2 June 5th 2014

  • Fixes bugs:
    • Type synonym improperly expanded #17
    • BlackBox for Signed maxBound and minBound generate incorrect VHDL. #19
    • Generate failure code in the VHDL for recSelError #23

0.3.1 May 15th 2014

  • New features:

    • Hardcode fromInteger for Signed and Unsigned #9
    • Better blackbox operation for vindex #12
    • Replace VHDL default hole by error hole #13
  • Fixes bugs:

    • Update GHC2Core.hs #1
    • primitives (clash.sized.vector) #2
    • Type families are not expanded #3
    • Incorrect vhdl generation for default value in blackbox #6
    • Missing begin keyword in Signed/Unsigned JSON files #16