BSD-2-Clause licensed by Christiaan Baaij
This version can be pinned in stack with:clash-lib-0.5.4@sha256:b4f9a4b6336f43180cb8633d801d8f53c7202ff0760eeb422491be314b3c28d8,5112
Module documentation for 0.5.4
Depends on 25 packages
(full list with versions):
aeson,
attoparsec,
base,
bytestring,
clash-prelude,
concurrent-supply,
containers,
deepseq,
directory,
errors,
fgl,
filepath,
hashable,
lens,
mtl,
pretty,
process,
template-haskell,
text,
time,
transformers,
unbound-generics,
unordered-containers,
uu-parsinglib,
wl-pprint-text clash-lib
- See the LICENSE file for license and copyright details
Changelog for the clash-lib
package
0.5.4
- New features:
- Add
~COMPNAME
tag: primitives get access to the component name in which they are instantiated
0.5.3 May 5th 2015
- New features:
TopEntity
wrappers are now specified as ANN
annotation pragmas
- Fixes bugs:
- Lost system1000 clock in VHDL generation… #53
flattenCallTree
sometimes introduces free variables
0.5.2 May 1st 2015
- New features:
- Generate wrappers around
topEntity
that have constant names and types
0.5.1 April 20th 2015
0.5 March 11th 2015
-
New features:
- Simplify BlackBox handling, and improve VHDL generation. #47
- Use unbound-generics. #48
-
Fixes bugs:
- VHDL generation error: wrapper for sum-of-products type. #44
0.4.1 February 4th 2015
- Fixes bugs:
- Treat BlackBox expressions as declarations when DC args. #37
- Don’t inline recursive closed bindings
0.4 November 17th 2014
-
New features:
- Support for clash-prelude 0.6
-
Fixes bugs:
- Ambiguous type: ‘std_logic_vector’ or ‘std_ulogic_vector’ #33
0.3.2 June 5th 2014
- Fixes bugs:
- VHDL array constant ambiguous #18
- Exception: can’t create selector #24
- Calls to
vhdlTypeMark
don’t result to inclusion of VHDL type in types.vhdl #28
0.3.1 May 15th 2014
-
New features:
- Make ANF lift non-representable values #7
- Hardcode
fromInteger
for Signed
and Unsigned
#9
- Replace VHDL default hole by error hole #13
-
Fixes bugs:
- Type families are not expanded #3
- Exception: CLaSH.Netlist.VHDL(512): fromSLV: Vector 13 Bool #5
- Incorrect vhdl generation for default value in blackbox #6
- Duplicate type names when multiple ADTs need the same amount of bits #8
- Circuit testbench generation with MAC example fails#15
-
Code improvements:
- Refactor Netlist/BlackBox #10
- CPP special-case conversion of
Control.Exception.Base.irrefutPatError
#11