Use new VHDL backend which outputs VHDL-93 instead of VHDL-2002: generated VHDL is now accepted by a larger number of tools.
Treat all so-called bottom values (error "FOO", let x = x in x, etc.) occuring in installed libraries as undefined.
Before, there were (very) rare situations where we couldn’t find the expressions belonging to a function and demanded a BlackBox, even though we knew the expression would be a bottom value.
Now, we stop demanding a BlackBox for such a function and simply treat it as undefined, thus allowing a greater range of circuit descriptions that we can compile.
0.5.9 June 26th 2015
New features:
Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
Fixes bugs:
--systemverilog switch incorrectly generates verilog code instead of systemverilog code
0.5.8 June 25th 2015
New features:
Support for copying string literals from Haskell to generated code
Support clash-prelude-0.9
Size at below which functions are always inlined is configurable, run with -clash-inline-below=N to set the size limit to N
0.5.7 June 3rd 2015
New features:
New Verilog backend, run :verilog in interactive mode, or --verilog for batch mode
Generated component names are prefixed by the name of the module containing the topEntity
0.5.6 May 18th 2015
New features:
Inlining limit is configurable, run with -clash-inline-limit=N to set the inlining limit to N
Specialisation limit is configurable, run with clash-spec-limit=N to set the inline limit to N
Debug level is configurable, run with -clash-debug <LEVEL> where <LEVEL> can be: DebugNone, DebugFinal, DebugName, DebugApplied, DebugAll. Be default, clash runs with DebugNone.
Fixes bugs:
Extend evaluator for GHC.Integer.Type.minusInteger and CLaSH.Promoted.Nat.SNat.
0.5.5 May 5th 2015
New features:
TopEntity wrappers are now specified as ANN annotation pragmas #42
0.5.4 May 1st 2015
New features:
Generate wrappers around topEntity that have constant names and types
0.5.3 April 24th 2015
Fixes bugs:
Fix bug where not enough array type definitions were created by the VHDL backend