clash-ghc
CAES Language for Synchronous Hardware
| Version on this page: | 0.6@rev:1 |
| LTS Haskell 24.28: | 1.8.4 |
| Stackage Nightly 2025-05-05: | 1.8.2@rev:1 |
| Latest on Hackage: | 1.8.4 |
clash-ghc-0.6@sha256:0fc6ef7850c34f7e3c199ad2ef1b19e37d84c7ba58dc713ddd639c1364684124,4826Module documentation for 0.6
There are no documented modules for this package.
clash-ghc - Haskell/GHC front-end for the CλaSH compiler
- See the LICENSE file for license and copyright details
- Contains code from the GHC compiler, see the LICENSE_GHC file for license and copyright details pertaining to that code.
CλaSH - A functional hardware description language
CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
-
Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).
-
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
-
Higher-order functions, with type inference, result in designs that are fully parametric by default.
-
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops. -
Support for multiple clock domains, with type safe clock domain crossing.
Support
For updates and questions join the mailing list [email protected] or read the forum
Changes
Changelog for the clash-ghc package
0.6 October 3rd 2015
- New features:
- Support
clash-prelude-0.10 - Pattern matching on
CLaSH.Sized.Vector’s:>is now supported - Unroll “definitions” of the following primitives:
fold,dfold,foldr
- Support
0.5.15 September 21st 2015
-
New features:
- Report simulation time in (System)Verilog assert messages
-
Fixes bugs:
- Performance bug: top-level definitions of type “Signal” erroneously inlined.
- Fix Index maxBound #79
0.5.14 September 14th 2015
-
New features:
- Completely unroll “definitions” of some higher-order primitives with non-representable argument or result vectors:
It is now possible to translate e.g.
f xs ys = zipWith ($) (map (+) xs) ys :: Vec 4 Int -> Vec 4 Int -> Vec 4 Int
- Completely unroll “definitions” of some higher-order primitives with non-representable argument or result vectors:
It is now possible to translate e.g.
-
Fixes bugs:
0.5.13 September 8th 2015
- Fixes bugs:
- Cannot translate GHC
MachLabelliteral - Maybe (Index n) not translatable to VHDL #75
- Cannot translate GHC
0.5.12 September 7th 2015
-
New features:
- Modest compilation time speed-up. Compilation time of the I2C module on my machine went down from 43s to 24s, and maximum memory usage went down from 840 MB to 700 MB.
-
Fixes bugs:
0.5.11 August 2nd 2015
- New features:
- Re-enable GHC’s strictness analysis pass, which improves dead-code removal, which hopefully leads to smaller circuits.
0.5.10 July 9th 2015
- New features:
- Use new VHDL backend which outputs VHDL-93 instead of VHDL-2002: generated VHDL is now accepted by a larger number of tools.
- Treat all so-called bottom values (
error "FOO",let x = x in x, etc.) occuring in installed libraries asundefined. Before, there were (very) rare situations where we couldn’t find the expressions belonging to a function and demanded a BlackBox, even though we knew the expression would be a bottom value. Now, we stop demanding a BlackBox for such a function and simply treat it asundefined, thus allowing a greater range of circuit descriptions that we can compile.
0.5.9 June 26th 2015
-
New features:
- Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
-
Fixes bugs:
--systemverilogswitch incorrectly generates verilog code instead of systemverilog code
0.5.8 June 25th 2015
- New features:
- Support for copying string literals from Haskell to generated code
- Support
clash-prelude-0.9 - Size at below which functions are always inlined is configurable, run with
-clash-inline-below=Nto set the size limit toN
0.5.7 June 3rd 2015
- New features:
- New Verilog backend, run
:verilogin interactive mode, or--verilogfor batch mode - Generated component names are prefixed by the name of the module containing the
topEntity
- New Verilog backend, run
0.5.6 May 18th 2015
-
New features:
- Inlining limit is configurable, run with
-clash-inline-limit=Nto set the inlining limit toN - Specialisation limit is configurable, run with
clash-spec-limit=Nto set the inline limit toN - Debug level is configurable, run with
-clash-debug <LEVEL>where<LEVEL>can be:DebugNone, DebugFinal, DebugName, DebugApplied, DebugAll. Be default,clashruns withDebugNone.
- Inlining limit is configurable, run with
-
Fixes bugs:
- Extend evaluator for
GHC.Integer.Type.minusIntegerandCLaSH.Promoted.Nat.SNat.
- Extend evaluator for
0.5.5 May 5th 2015
- New features:
TopEntitywrappers are now specified asANNannotation pragmas #42
0.5.4 May 1st 2015
- New features:
- Generate wrappers around
topEntitythat have constant names and types
- Generate wrappers around
0.5.3 April 24th 2015
- Fixes bugs:
- Fix bug where not enough array type definitions were created by the VHDL backend
0.5.2 April 21st 2015
- Use latest ghc-typelits-natnormalise
0.5.1 April 20th 2015
- New features:
- GHC 7.10 support
- Update to clash-prelude 0.7.2
- Use http://hackage.haskell.org/package/ghc-typelits-natnormalise typechecker plugin for better type-level natural number handling
0.5 March 11th 2015
- New features:
- SystemVerilog backend. #45
0.4.1 February 4th 2015
- Include bug fixes from clash-lib 0.4.1
0.4 November 17th 2014
-
New features:
- Support for clash-prelude 0.6
-
Fixes bugs:
- clash-ghc ignores “-package-db” flag #35
0.3.3 August 12th 2014
- Fixes bugs:
- Compile with GHC 7.8.3 #31
0.3.2 June 5th 2014
- Fixes bugs:
0.3.1 May 15th 2014
-
New features:
-
Fixes bugs: