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CλaSH - A functional hardware description language
CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
Strongly typed (like VHDL), yet with a very high degree of type inference,
which enables both safe and fast prototying using consise descriptions (like
Verilog)
Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are
fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals.
Support for multiple clock domains, with type safe clock domain crossing.
Performance bug: top-level definitions of type “Signal” erroneously inlined.
0.5.12 September 14th 2015
New features:
Completely unroll “definitions” of some higher-order primitives with non-representable argument or result vectors:
It is now possible to translate e.g. f xs ys = zipWith ($) (map (+) xs) ys :: Vec 4 Int -> Vec 4 Int -> Vec 4 Int
Fixes bugs:
topLet transformation erroneously not performed in a top-down traversal
Specialisation limit unchecked on types and constants
CLaSH fails to generate VHDL when map is applied #78
0.5.11 September 7th 2015
Fixes bugs:
Clash running out of memory on Simple-ish project #70
CLaSH.Sized.Vector.:> was not allowed as a function argument to HO-primitives
0.5.10 August 2nd 2015
Fixes bugs:
Make testbench generation deterministic
Compile against unbound-generics-0.2
0.5.9 July 9th 2015
Fixes bugs:
coreView didn’t look through newtypes of the form: newtype Foo a = MkFoo (Maybe a)
0.5.8 June 26th 2015
Fixes bugs:
Allow text and tags in ~SIGD black box construct
0.5.7 June 25th 2015
New features:
Support for copying string literals from Haskell to generated code
Collect and copy data-files
Fixes bugs:
Signals declared twice when not using a clock-generating component #60
This piece of code eat up all CPU when generating verilog #62
0.5.6 June 3rd 2015
New features:
Support Verilog backend
Generated component names are prefixed by the name of the module containing the topEntity
0.5.5 May 18th 2015
New features:
Make inlining and specialisation limit configurable
Make debug message level configurable
Fixes bugs:
Netlist: ensure that the arguments of a component instantiation are always simple variables
CaseCon transformation: ensure that we run the compile-time evaluator on the subject before handling the one-alternative case
Emit a warning if a function remains recursive, instead of producing an error: compilation can still be successful if the function is an argument to a higher-order blackbox that doesn’t use the function.
Emit a warning if inlining limit is reached, instead of producing an error: compilation can still be successful if the function is an argument to a higher-order blackbox that doesn’t use the function.
Always inline terms that have a type of kind Constraint
0.5.4 May 10th 2015
New features:
Add ~COMPNAME tag: primitives get access to the component name in which they are instantiated
0.5.3 May 5th 2015
New features:
TopEntity wrappers are now specified as ANN annotation pragmas
